Release for sockit_owm

1-wire (onewire) master written in Verilog HDL sockit_owm has been released.

The source code is available here:

https://github.com/jeras/sockit_owm
http://opencores.org/project,sockit_owm

RTL features:

• small RTL, should fit into a CPLD
• Avalon MM bus, Wishbone compatible with a simple adapter
• timed reset, presence, write/read bit transfers
• overdrive
• power supply (strong pull-up)

Altera SOPC Builder integration

Altera Nios II EDS integration:

• port of the 1-wire open domain kit version 3.10b
• interrup driven or polling driver
• uCOS-II support (only partially tested)

Detailed documentation is provided inside the package. Please read it, it covers almost anything, that can be said about the project.

The module was developed using open source tools (Icarus Verilog, GTKWave) but it was tested on the Terasic DE1 board (a demo for the board is included in the package).